Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
R01UH0042EJ0500 Rev.5.00 Page 745 of 1513
Aug 12, 2011
17.6.5 UART transmission
A high level is output to the TXDCn pin by setting the UCnCTL0.UCnPWR bit to 1.
Next, the transmission enabled status is set by setting the UCnCTL0.UCnTXE bit to 1, and transmission is started by
writing transmit data to the UCnTX register. The start bit, parity bit, and stop bit are automatically added.
Since the CTS (transmit enable signal) input pin is not provided in UARTCn, use a port to check that reception is
enabled at the transmit destination.
The data in the UCnTX register is transferred to the UARTCn transmit shift register upon the start of the transmit
operation.
A transmission enable interrupt request signal (INTUCnT) is generated upon completion of transmission of the data of
the UCnTX register to the UARTCn transmit shift register, and thereafter the contents of the UARTCn transmit shift register
are output to the TXDCn pin.
Write of the next transmit data to the UCnTX register is enabled after the INTUCnT signal is generated.
Figure 17-12. UART Transmission
Start
bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity
bit
Stop
bit
INTUCnT
TXDCn
Remark LSB first