Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
R01UH0042EJ0500 Rev.5.00 Page 744 of 1513
Aug 12, 2011
17.6.4 SBF reception
The reception wait status is entered by setting the UCnCTL0.UCnPWR bit to 1 and then setting the UCnCTL0.UCnRXE
bit to 1.
The SBF reception wait status is set by setting the SBF reception trigger (UCnOPT0.UCnSRT bit) to 1.
In the SBF reception wait status, similarly to the UART reception wait status, the RXDCn pin is monitored and start bit
detection is performed.
Following detection of the start bit, reception is started and the internal counter counts up according to the set baud rate.
When a stop bit is received, if the SBF width is 11 or more bits, normal processing is judged and a reception completion
interrupt request signal (INTUCnR) is output. The UCnOPT0.UCnSRF bit is automatically cleared and SBF reception ends.
Error detection for the UCnSTR.UCnOVE, UCnSTR.UCnPE, and UCnSTR.UCnFE bits is suppressed and UART
communication error detection processing is not performed. Moreover, data transfer of the UARTCn reception shift
register and UCnRX register is not performed and FFH, the initial value, is held. If the SBF width is 10 or fewer bits,
reception is terminated as error processing without outputting an interrupt, and the SBF reception mode is returned to.
The UCnSRF bit is not cleared at this time.
Cautions 1. If SBF is transmitted during a data reception, a framing error occurs.
2. Do not set the SBF reception trigger bit (UCnSRT) and SBF transmission trigger bit (UCnSTT) to 1
during an SBF reception (UCnSRF = 1).
Figure 17-11. SBF Reception
(a) Normal SBF reception (detection of stop bit in more than 10.5 bits)
UCnSRF
RXDCn
123456
11.5
7 8 9 10 11
INTUCnR
interrupt
(b) SBF reception error (detection of stop bit in 10.5 or fewer bits)
UCnSRF
RXDCn 123456
10.5
78910
INTUCnR
interrupt