Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
R01UH0042EJ0500 Rev.5.00 Page 742 of 1513
Aug 12, 2011
Figure 17-9. LIN Reception Manipulation Outline
Reception interrupt (INTUCnR)
Edge detection
Capture timer
Disable
Disable
Enable
RXDCn (input)
Enable
Note 2
13 bits
SBF
reception
Note 3
Note 4
Note 1
SF reception
ID reception
Data
transmission
Data
transmission
Note 5
Data transmission
LIN
bus
Wake-up
signal
frame
Sync
break
field
Sync
field
Identifier
field
DATA
field
DATA
field
Check
SUM
field
Notes 1. The wakeup signal is sent by the pin edge detector, UARTCn is enabled, and the SBF reception
mode is set.
2. The receive operation is performed until detection of the stop bit. Upon detection of SBF reception
of 11 or more bits, normal SBF reception end is judged, and an interrupt signal is output. Upon
detection of SBF reception of less than 11 bits, an SBF reception error is judged, no interrupt signal
is output, and the mode returns to the SBF reception mode.
3. If SBF reception ends normally, an interrupt request signal is output. The timer is enabled by an SBF
reception completion interrupt. Moreover, error detection for the UCnSTR.UCnOVE,
UCnSTR.UCnPE, and UCnSTR.UCnFE bits is suppressed and UART communication error
detection processing and UARTCn receive shift register and data transfer of the UCnRX register are
not performed. The UARTCn receive shift register holds the initial value, FFH.
4. The RXDCn pin is connected to TI (capture input) of the timer, the transfer rate is calculated, and the
baud rate error is calculated. The value of the UCnCTL2 register obtained by correcting the baud
rate error after dropping UARTC enable is set again, causing the status to become the reception
status.
5. Check-sum field distinctions are made by software. UARTCn is initialized following CSF reception,
and the processing for setting the SBF reception mode again is performed by software.