Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
R01UH0042EJ0500 Rev.5.00 Page 733 of 1513
Aug 12, 2011
Table 17-2. Relationship Between Register Setting and Data Format
Register Setting Data Format
UCnCTL0 UCnOPT1
UCnCL UCnPS1 UCnPS0 UCnSL UCnEBE
D0 to D6 D7 D8 D9 D10
0 0 0 Data Stop
− − −
0 Other than 00 Data Parity Stop
− −
1 0 0 Data Data Stop
− −
1 Other than 00
0 0
Data Data Parity Stop
−
0 0 0 Data Stop Stop
− −
0 Other than 00 Data Parity Stop Stop
−
1 0 0 Data Data Stop Stop
−
1 Other than 00
1 0
Data Data Parity Stop Stop
0 0 0 Data Stop
− − −
0 Other than 00 Data Parity Stop
− −
1 0 0 Data Data Data Stop
−
1 Other than 00
0 1
Data Data Parity Stop
−
0 0 0 Data Stop Stop
− −
0 Other than 00 Data Parity Stop Stop
−
1 0 0 Data Data Data Stop Stop
1 Other than 00
1 1
Data Data Parity Stop Stop
Remark Data: Data bit
Stop: Stop bit
Parity: Parity bit