Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
R01UH0042EJ0500 Rev.5.00 Page 731 of 1513
Aug 12, 2011
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UCnSLS2
1
1
1
0
0
0
0
1
UCnSLS1
0
1
1
0
0
1
1
0
UCnSLS0
1
0
1
0
1
0
1
0
13-bit output (reset value)
14-bit output
15-bit output
16-bit output
17-bit output
18-bit output
19-bit output
20-bit output
SBF transmission length selection
• The output level of the TXDCn pin can be inverted using the UCnTDL bit.
• This register can be set when the UCnPWR bit = 0 or when the UCnTXE bit = 0.
This register can be set when the UCnPWR bit = 0 or when the UCnTXE bit = 0.
Normal output of transfer data
Inverted output of transfer data
UCnTDL
0
1
Transmit data level bit
• The input level of the RXDCn pin can be inverted using the UCnRDL bit.
• This register can be set when the UCnPWR bit = 0 or the UCnRXE bit = 0.
Normal input of transfer data
Inverted input of transfer data
UCnRDL
0
1
Receive data level bit