Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
R01UH0042EJ0500 Rev.5.00 Page 730 of 1513
Aug 12, 2011
(4) UARTCn option control register 0 (UCnOPT0)
The UCnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTCn register.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 14H.
(1/2)
UCnSRF
When the UCnCTL0.UCnPWR bit = UCnCTL0.UCnRXE bit = 0 are set, or
upon normal end of SBF reception.
During SBF reception
UCnSRF
0
1
SBF reception flag
UCnOPT0
(n = 0 to 4)
UCnSRT UCnSTT UCnSLS2 UCnSLS1 UCnSLS0 UCnTDL UCnRDL
654321
After reset: 14H R/W Address: UC0OPT0 FFFFFA03H, UC1OPT0 FFFFFA13H,
UC2OPT0 FFFFFA23H, UC3OPT0 FFFFFA33H,
UC4OPT0 FFFFFA43H
SBF reception trigger
UCnSRT
0
1
SBF reception trigger
• SBF (Sync Brake Field) reception is judged during LIN communication.
• The UCnSRF bit is held at 1 when an SBF reception error occurs, and then SBF
reception is started again.
• The UCnSRF bit is a read-only bit.
• This is the SBF reception trigger bit during LIN communication, and when read,
“0” is always read. For SBF reception, set the UCnSRT bit (to 1) to enable SBF
reception.
• Set the UCnSRT bit after setting the UCnPWR bit = UCnRXE bit = 1.
• This is the SBF transmission trigger bit during LIN communication, and when read,
“0” is always read.
• Set the UCnSTT bit after setting the UCnPWR bit = UCnTXE bit = 1.
SBF transmission trigger
UCnSTT
0
1
SBF transmission trigger
<7> 0
−
−
Caution Do not set the UCnSRT and UCnSTT bits (to 1) during SBF reception (UCnSRF bit = 1).