Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
R01UH0042EJ0500 Rev.5.00 Page 729 of 1513
Aug 12, 2011
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7 bits
8 bits
UCnCL
0
1
Specification of data character length of 1 frame of transmit/receive data
• This register can be rewritten only when the UCnPWR bit = 0 or the UCnTXE bit =
the UCnRXE bit = 0.
• When transmission and reception are performed in the LIN format, set the UCnCL
bit to 1.
1 bit
2 bits
UCnSL
0
1
Specification of length of stop bit for transmit data
This register can be rewritten only when the UCnPWR bit = 0 or the UCnTXE bit =
the UCnRXE bit = 0.
• This register is rewritten only when the UCnPWR bit = 0 or the UCnTXE bit = the
UCnRXE bit = 0.
•
If “Reception with 0 parity” is selected during reception, a parity check is not performed.
Therefore, the UCnSTR.UCnPE bit is not set.
• When transmission and reception are performed in the LIN format, clear the
UCnPS1 and UCnPS0 bits to 00.
No parity output
0 parity output
Odd parity output
Even parity output
Reception with no parity
Reception with 0 parity
Odd parity check
Even parity check
UCnPS1
0
0
1
1
Parity selection during transmission Parity selection during reception
UCnPS0
0
1
0
1
MSB-first transfer
LSB-first transfer
UCnDIR
0
1
Transfer direction selection
• This register can be rewritten only when the UCnPWR bit = 0 or the UCnTXE bit =
the UCnRXE bit = 0.
• When transmission and reception are performed in the LIN format, set the UCnDIR
bit to 1.
Remark For details of parity, see 17.6.9 Parity types and operations.
(2) UARTCn control register 1 (UCnCTL1)
For details, see 17.7 (2) UARTCn control register 1 (UCnCTL1).
(3) UARTCn control register 2 (UCnCTL2)
For details, see 17.7 (3) UARTCn control register 2 (UCnCTL2).