Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
R01UH0042EJ0500 Rev.5.00 Page 728 of 1513
Aug 12, 2011
17.4 Registers
(1) UARTCn control register 0 (UCnCTL0)
The UCnCTL0 register is an 8-bit register that controls the UARTCn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 10H.
(1/2)
UCnPWR
Disable UCRTCn operation (UCRTCn reset asynchronously)
Enable UCRTCn operation
UCnPWR
0
1
UCRTCn operation control
UCnCTL0
(n = 0 to 4)
UCnTXE UCnRXE UCnDIR UCnPS1 UCnPS0 UCnCL UCnSL
<6> <5> <4> 3 2 1
After reset: 10H R/W Address:
UC0CTL0 FFFFFA00H, UC1CTL0 FFFFFA10H,
UC2CTL0 FFFFFA20H, UC3CTL0 FFFFFA30H,
UC4CTL0 FFFFFA40H
The UARTCn operation is controlled by the UCnPWR bit. The TXDCn pin output
is fixed to high level by clearing the UCnPWR bit to 0 (fixed to low level if
UCnOPT0.UCnTDL bit = 1).
Disable transmission operation
Enable transmission operation
UCnTXE
0
1
Transmission operation enable
• To start transmission, set the UCnPWR bit to 1 and then set the UCnTXE bit to 1.
To stop transmission, clear the UCnTXE bit to 0 and then UCnPWR bit to 0.
• To initialize the transmission unit, clear the UCnTXE bit to 0, wait for two cycles of
the base clock, and then set the UCnTXE bit to 1 again. Otherwise, initialization
may not be executed (for the base clock, see 17.7 (1) (a) Base clock).
Disable reception operation
Enable reception operation
UCnRXE
0
1
Reception operation enable
• To start reception, set the UCnPWR bit to 1 and then set the UCnRXE bit to 1.
To stop reception, clear the UCnRXE bit to 0 and then UCnPWR bit to 0.
• To initialize the reception unit, clear the UCnRXE bit to 0, wait for two periods of
the base clock, and then set the UCnRXE bit to 1 again. Otherwise, initialization
may not be executed (for the base clock, see 17.7 (1) (a) Base clock).
<7> 0