Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
R01UH0042EJ0500 Rev.5.00 Page 725 of 1513
Aug 12, 2011
17.3.3 Mode switching between UARTC2 and CSIF3
In the V850ES/JG3-H and V850ES/JH3-H, UARTC2 and CSIF3 share of the same pin and therefore cannot be used
simultaneously. Set UARTC2 in advance, using the PMC9, PFC9 and PFCE9 registers, before use.
Caution The transmit/receive operation of UARTC2 and CSIF3 is not guaranteed if these functions are
switched during transmission or reception. Be sure to disable the one that is not used.
Figure 17-4. UARTC2 and CSIF3 Mode Switch Settings
PMC9
After reset: 0000H R/W Address: FFFFF452H, FFFFF453H
PMC97 PMC96 PMC95 PMC94 PMC93 PMC92 PMC91 PMC90
PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 PMC99 PMC98
89101112131415
PFC9
After reset: 0000H R/W Address: FFFFF472H, FFFFF473H
PFC915 PFC914 PFC913 PFC912 PFC911 PFC910 PFC99 PFC98
PFC97 PFC96 PFC95 PFC94 PFC93 PFC92 PFC91 PFC90
89101112131415
PFCE915 PFCE914 0 0 PFCE911 PFCE910 PFCE99 PFCE98
PFCE97 PFCE96 PFCE95 PFCE94 PFCE93 PFCE92 PFCE91 PFCE90
89101112131415
PFCE9
After reset: 0000H R/W Address: FFFFF712H, FFFFF713H
Port I/O mode
RXDC1 (UARTC1)
SCL02 (I
2
C02)
PMC90
0
1
1
Operation mode
PFCE90
×
0
1
PFC90
×
1
0
Port I/O mode
TXDC1 (UARTC1)
SDA02 (I
2
C02)
PMC91
0
1
1
Operation mode
PFCE91
×
0
1
PFC91
×
1
0
Remark × = don’t care