Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
R01UH0042EJ0500 Rev.5.00 Page 721 of 1513
Aug 12, 2011
17.2 Configuration
The block diagram of the UARTCn is shown below.
Figure 17-1. Block Diagram of Asynchronous Serial Interface Cn
Internal bus
Internal bus
Receive
shift register
UCnRX
Filter
Selector
UCnTX
Transmit
shift register
Transmission
controller
Reception
controller
Selector
Baud rate
generator
Baud rate
generator
INTUCnR
INTUCnT
TXDCn
RXDCn
f XX to f XX /2
10
ASCKC0
Note
Reception unit
Transmission
unit
Clock
selector
UCnOPT0
UCnCTL1
UCnCTL2
UCnSTR
UCnCTL0
Note UARTC0 only
Remarks 1. n = 0 to 4
2. For the configuration of the baud rate generator, see Figure 17-19.
UARTCn includes the following hardware.
Table 17-1. Configuration of UARTCn
Item Configuration
Registers UARTCn control register 0 (UCnCTL0)
UARTCn control register 1 (UCnCTL1)
UARTCn control register 2 (UCnCTL2)
UARTCn option control register 0 (UCnOPT0)
UARTCn option control register 1 (UCnOPT1)
UARTCn status register (UCnSTR)
UARTCn receive shift register
UARTCn receive data register (UCnRX)
UARTCn transmit shift register
UARTCn transmit data register (UCnTX)