Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
R01UH0042EJ0500 Rev.5.00 Page 720 of 1513
Aug 12, 2011
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
The V850ES/JG3-H and V850ES/JH3-H have a 5-channel UARTC.
17.1 Features
{ Transfer rate: 300 bps to 3 Mbps (using internal system clock of 24 MHz and dedicated baud rate generator)
{ Full-duplex communication: Internal UARTCn receive data register (UCnRX)
Internal UARTCn transmit data register (UCnTX)
{ 2-pin configuration: TXDCn: Transmit data output pin
RXDCn: Receive data input pin
{ Reception error detection function
• Parity error
• Framing error
• Overrun error
{ Interrupt sources: 2 types
• Reception completion interrupt (INTUCnR): This interrupt occurs upon transfer of receive data from the receive
shift register to the receive data register after serial transfer is
complete, in the reception enabled status.
• Transmission enable interrupt (INTUCnT): This interrupt occurs upon transfer of transmit data from the
transmit data register to the transmit shift register in the
transmission enabled status.
{ Character length: 7 to 9 bits
{ Parity function: Odd, even, 0, none
{ Transmission stop bit: 1, 2 bits
{ On-chip dedicated baud rate generator
{ MSB-/LSB-first transfer selectable
{ Transmit/receive data inverted input/output possible
{ SBF (Sync Break Field) transmission in the LIN (Local Interconnect Network) communication format
• 13 to 20 bits selectable for the SBF transmission
• Recognition of 11 bits or more possible for SBF reception
• SBF reception flag provided
Remark n = 0 to 4