Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER
R01UH0042EJ0500 Rev.5.00 Page 688 of 1513
Aug 12, 2011
(3) A/D converter mode register 2 (ADA0M2)
The ADA0M2 register specifies the hardware trigger mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0ADA0M2 0 0 0 00 ADA0TMD1 ADA0TMD0
ADA0TMD1
0
0
1
1
ADA0TMD0
0
1
0
1
Specification of hardware trigger mode
External trigger mode (when ADTRG pin valid edge is detected)
Timer trigger mode 0
(when INTTAA2CC0 interrupt request is generated)
Timer trigger mode 1
(when INTTAA2CC1 interrupt request is generated)
Timer trigger mode 2 (TQTADT0 signal)
After reset: 00H R/W Address: FFFFF203H
65432107
Cautions 1. In the following modes, write data to the ADA0M2 register while A/D conversion is
stopped (ADA0M0.ADA0CE bit = 0), and then enable the A/D conversion operation
(ADA0CE bit = 1).
• Normal conversion mode
• One-shot select mode/one-shot scan mode in high-speed conversion mode
2. Be sure to clear bits 7 to 2 to “0”.