Datasheet
V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER
R01UH0042EJ0500 Rev.5.00 Page 687 of 1513
Aug 12, 2011
Table 15-3. Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1 Bit = 1)
A/D Conversion Time ADA0FR3 to
ADA0FR0
Bits
Conversion Time
(+ Stabilization Time)
48 MHz 32 MHz 24 MHz
0000 52/fXX (+26/fXX) Setting prohibited Setting prohibited 2.17
μ
s
0001 104/fXX (+52/fXX) 2.17
μ
s 3.25
μ
s 4.33
μ
s
0010 156/fXX (+78/fXX) 3.25
μ
s 4.88
μ
s 6.50
μ
s
0011 208/fXX (+100/fXX) 4.33
μ
s 6.50
μ
s 8.67
μ
s
0100 260/fXX (+100/fXX) 5.42
μ
s 8.13
μ
s Setting prohibited
0101 312/fXX (+100/fXX) 6.50
μ
s 9.75
μ
s Setting prohibited
0110 364/fXX (+100/fXX) 7.58
μ
s Setting prohibited Setting prohibited
0111 416/fXX (+100/fXX) 8.67
μ
s Setting prohibited Setting prohibited
1000 468/fXX (+100/fXX) 9.75
μ
s Setting prohibited Setting prohibited
1001 520/fXX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited
1010 572/fXX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited
1011 624/fXX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited
1100 676/fXX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited
1101 728/fXX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited
1110 780/fXX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited
1111 832/fXX (+100/fXX) Setting prohibited Setting prohibited Setting prohibited
Other than above Setting prohibited
Remark Stabilization time: A/D converter setup time (1
μ
s or longer)
Conversion time: Actual A/D conversion time (2.17 to 9.75
μ
s)
f
XX: Main clock frequency
In the high-speed conversion mode, the conversion is started after the stabilization time elapses after the
ADA0M0.ADA0CE bit is set to 1, and A/D conversion is performed only during the conversion time (2.17 to 9.75
μ
s). The A/D conversion end interrupt request signal (INTAD) is generated immediately after the conversion
ends.
In continuous conversion mode, the stabilization time is inserted only before the first conversion, and not
inserted after the second conversion (the A/D converter remains running).
Cautions 1. Set as 2.17
μ
s ≤ conversion time ≤ 9.75
μ
s.
2. In the high-speed conversion mode, rewriting of the ADA0M0, ADA0M2, ADA0S, ADA0PFM,
and ADA0PFT registers and trigger input are prohibited during the stabilization time.