Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER
R01UH0042EJ0500 Rev.5.00 Page 686 of 1513
Aug 12, 2011
Table 15-2. Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0)
A/D Conversion Time ADA0FR3 to
ADA0FR0
Bits
Stabilization Time
+ Conversion Time + Wait Time
48 MHz 32 MHz 24 MHz
0000 26/fXX + 52/fXX + 54/fXX Setting prohibited Setting prohibited 5.50 μ s
0001 52/fXX + 104/fXX + 106/fXX 5.46 μ s 8.19 μ s Setting prohibited
0010 78/fXX + 156/fXX + 158/fXX 8.17 μ s Setting prohibited Setting prohibited
0011 100/fXX + 208/fXX + 210/fXX Setting prohibited Setting prohibited Setting prohibited
0100 100/fXX + 260/fXX + 262/fXX Setting prohibited Setting prohibited Setting prohibited
0101 100/fxx + 312/fxx + 314/fXX Setting prohibited Setting prohibited Setting prohibited
0110 100/fxx + 364/fxx + 366/fXX Setting prohibited Setting prohibited Setting prohibited
0111 100/fXX + 416/fXX + 418/fXX Setting prohibited Setting prohibited Setting prohibited
1000 100/fXX + 468/fXX + 470/fXX Setting prohibited Setting prohibited Setting prohibited
1001 100/fXX + 520/fXX + 522/fXX Setting prohibited Setting prohibited Setting prohibited
1010 100/fXX + 572/fXX + 574/fXX Setting prohibited Setting prohibited Setting prohibited
1011 100/fXX + 624/fXX + 626/fXX Setting prohibited Setting prohibited Setting prohibited
1100 100/fXX + 676/fXX + 678/fXX Setting prohibited Setting prohibited Setting prohibited
1101 100/fXX + 728/fXX + 730/fXX Setting prohibited Setting prohibited Setting prohibited
1110 100/fXX + 780/fXX + 782/fXX Setting prohibited Setting prohibited Setting prohibited
1111 100/fXX + 832/fXX + 834/fXX Setting prohibited Setting prohibited Setting prohibited
Other than above Setting prohibited
Remark Stabilization time: A/D converter setup time (1
μ s or longer)
Conversion time: Actual A/D conversion time (2.17 to 9.75 μ s)
Wait time: Wait time inserted before the next conversion
f
XX: Main clock frequency
In the normal conversion mode, the conversion is started after the stabilization time elapses after the
ADA0M0.ADA0CE bit is set to 1, and A/D conversion is performed only during the conversion time (2.17 to 9.75
μ s). Operation is stopped after the conversion ends and the A/D conversion end interrupt request signal
(INTAD) is generated after the wait time elapses.
Because the conversion operation is stopped during the wait time, operating current can be reduced.
Cautions 1. Set as 2.17
μ s ≤ conversion time ≤ 9.75 μ s.
2. During A/D conversion, if the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT
registers are written or a trigger is input, reconversion is carried out. However, if the
stabilization time end timing conflicts with writing to these registers, or if the stabilization
time end timing conflicts with the trigger input, a stabilization time of 64 clocks is
reinserted.
If a conflict occurs again with the reinserted stabilization time end timing, the stabilization
time is reinserted. Therefore do not set the trigger input interval and control register write
interval to 64 clocks or lower.