Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 15 A/D CONVERTER
R01UH0042EJ0500 Rev.5.00 Page 683 of 1513
Aug 12, 2011
15.4 Registers
The A/D converter is controlled by the following registers.
• A/D converter mode registers 0, 1, 2 (ADA0M0, ADA0M1, ADA0M2)
• A/D converter channel specification register 0 (ADA0S)
• Power-fail compare mode register (ADA0PFM)
The following registers are also used.
• A/D conversion result register n (ADA0CRn)
• A/D conversion result register nH (ADA0CRnH)
• Power-fail compare threshold value register (ADA0PFT)
(1) A/D converter mode register 0 (ADA0M0)
The ADA0M0 register is an 8-bit register that specifies the operation mode and controls conversion operations.
This register can be read or written in 8-bit or 1-bit units. However, the ADA0EF bit is read-only.
Reset sets this register to 00H.
(1/2)
ADA0CE
ADA0CE
0
1
Stops A/D conversion
Enables A/D conversion
A/D conversion control
ADA0M0 0
ADA0MD1 ADA0MD0 ADA0ETS1 ADA0ETS0 ADA0TMD ADA0EF
ADA0MD1
0
0
1
1
ADA0MD0
0
1
0
1
Continuous select mode
Continuous scan mode
One-shot select mode
One-shot scan mode
Specification of A/D converter operation mode
After reset: 00H R/W Address: FFFFF200H
< >
< >
ADA0ETS1
0
0
1
1
ADA0ETS0
0
1
0
1
No edge detection
Falling edge detection
Rising edge detection
Detection of both rising and falling edges
Specification of external trigger (ADTRG pin) input valid edge