Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2
R01UH0042EJ0500 Rev.5.00 Page 671 of 1513
Aug 12, 2011
(2) Watchdog timer enable register (WDTE)
The counter of watchdog timer 2 is cleared and counting restarted by writing “ACH” to the WDTE register.
The WDTE register can be read or written in 8-bit units.
Reset sets this register to 9AH.
WDTE
After reset: 9AH R/W Address: FFFFF6D1H
Cautions 1. When a value other than “ACH” is written to the WDTE register, an overflow signal is
forcibly output.
2. When a 1-bit memory manipulation instruction is executed for the WDTE register, an
overflow signal is forcibly output.
3. To intentionally generate an overflow signal, write a value other than “ACH” to the WDTE
register once, or write data to the WDTM2 register twice.
However, when the operation of watchdog timer 2 is set to be stopped, an overflow signal is
not generated even if data is written to the WDTM2 register twice, or a value other than
“ACH” is written to the WDTE register once.
4. The read value of the WDTE register is “9AH” (which differs from written value “ACH”).
13.4 Operation
Watchdog timer 2 automatically starts in the reset mode following reset release.
The WDTM2 register can be written to only once following reset using byte access. To use watchdog timer 2, write the
operation mode and the interval time to the WDTM2 register using an 8-bit memory manipulation instruction. After this,
the operation of watchdog timer 2 cannot be stopped.
The WDTM2.WDCS24 to WDTM2.WDCS20 bits are used to select the watchdog timer 2 loop detection time interval.
Writing ACH to the WDTE register clears the counter of watchdog timer 2 and starts the count operation again. After
the count operation has started, write ACH to WDTE within the loop detection time interval.
If the time interval expires without ACH being written to the WDTE register, a reset signal (WDT2RES) or a non-
maskable interrupt request signal (INTWDT2) is generated, depending on the set values of the WDTM2.WDM21 and
WDTM2.WDM20 bits.
When the WDTM2.WDM21 bit is set to 1 (reset mode), if a WDT overflow occurs during oscillation stabilization after a
reset or standby is released, no internal reset will occur and the CPU clock will switch to the internal oscillation clock.
To not use watchdog timer 2, write 00H to the WDTM2 register.
For the non-maskable interrupt servicing while the non-maskable interrupt request mode is set, see 23.2.2 (2) From
INTWDT2 signal.