Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2
R01UH0042EJ0500 Rev.5.00 Page 669 of 1513
Aug 12, 2011
13.3 Registers
(1) Watchdog timer mode register 2 (WDTM2)
The WDTM2 register sets the overflow time and operation clock of watchdog timer 2.
This register can be read or written in 8-bit units. This register can be read any number of times, but it can be
written only once following reset release.
Reset sets this register to 67H.
Caution Accessing the WDTM2 register is prohibited in the following statuses. For details, see 3.4.9 (2)
Accessing specific on-chip peripheral I/O registers.
• When the CPU operates on the subclock and the main clock oscillation is stopped
• When the CPU operates on the internal oscillation clock
0WDTM2 WDM21 WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20
After reset: 67H R/W Address: FFFFF6D0H
Stops operation
Non-maskable interrupt request mode
(generation of INTWDT2 signal)
Reset mode (generation of WDT2RES signal)
WDM21
0
0
1
WDM20
0
1
–
Selection of operation mode of watchdog timer 2
Cautions 1. For details of the WDCS20 to WDCS24 bits, see Table 13-2 Watchdog Timer 2 Clock
Selection.
2. Although watchdog timer 2 can be stopped just by stopping operation of the internal
oscillator, clear the WDTM2 register to 00H to securely stop the timer (to avoid selection of
the main clock or subclock due to an erroneous write operation).
3. If the WDTM2 register is rewritten twice after reset, an overflow signal is forcibly generated
and the counter is reset.
4. To intentionally generate an overflow signal, write data to the WDTM2 register twice, or
write a value other than “ACH” to the WDTE register once.
However, when the operation of watchdog timer 2 is set to be stopped, an overflow signal
is not generated even if data is written to the WDTM2 register twice, or a value other than
“ACH” is written to the WDTE register once.
5. To stop the operation of watchdog timer 2, set the RCM.RSTOP bit to 1 (to stop the
internal oscillator) and write 00H in the WDTM2 register. If the RCM.RSTOP bit cannot be
set to 1, set the WDCS23 bit to 1 (2
n
/fXX is selected and the clock can be stopped in the
IDLE1, IDLW2, sub-IDLE, and subclock operation modes).