Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER
R01UH0042EJ0500 Rev.5.00 Page 665 of 1513
Aug 12, 2011
(3) DEV bit
The DEV bit determines when the setting by the F6 to F0 bits is enabled.
The value set by the F6 to F0 bits is reflected upon the next timing, but not to the RC1SUBC count value every time.
Table 12-6. DVE Bit Setting
DEV Bit Value Timing of Reflecting Value to RC1SUBC
0 When RC1SEC is 00, 20, or 40 seconds.
1 When RC1SEC is 00 seconds.
[Example when 0010101B is set to F6 to F0 bits]
• If the DEV bit is 0
The RC1SUBC count value is 32,808 at 00, 20, or 40 seconds.
Otherwise, it is 32,768.
• IF DEV bit is 1
The RC1SUBC count value is 32,808 at 00 seconds.
Otherwise, it is 32,768.
As described above, the RC1SUBC count value is corrected every 20 seconds or 60 seconds, instead of every
second, in order to match the RC1SUBC count value with the deviation width of the resonator.
The range in which the resonator frequency can be actually corrected is shown below.
• If the DEV bit is 0: 32.76180000 kHz to 32.77420000 kHz
• If the DEV bit is 1: 32.76593333 kHz to 32.77006667 kHz
The range in which the frequency can be corrected when the DEV bit is 0 is three times wider than when the DEV
bit is 1.
However, the accuracy of setting the frequency when the DEV bit is 1 is three times that when the DEV bit is 0.
Tables 12-7 and 12-8 show the setting values of the DEV, and F6 to F0 bits, and the corresponding frequencies that
can be corrected.