Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 66 of 1513
Aug 12, 2011
3.4.3 Memory map
The areas shown below are reserved in the V850ES/JG3-H and V850ES/JH3-H.
Figure 3-2. Data Memory Map (Physical Addresses)
(80 KB)
Use prohibited
External memory area
(8 MB)
Internal ROM area
Note 5
(1 MB)
External memory area
(1 MB)
Internal RAM area
(60 KB)
On-chip peripheral I/O area
(4 KB)
CS3
CS2
CS0
External memory area
(4 MB)
External memory area
(2 MB)
(2 MB)
CS1
Note 1
Use prohibited
Note 2
Programmable peripheral
I/O area
Note 3
or
use prohibited
Note 4
Data-only RAM area
(8 KB)
Use prohibited
Use prohibited
USB function area
00000000H
001FFFFFH
00200000H
003FFFFFH
00400000H
007FFFFFH
00800000H
00FFFFFFH
03FFFFFFH 03FFFFFFH
03FFF000H
03FFEFFFH
03FF0000H
003FFFFFH
03FEF000H
03FEEFFFH
03FEFFFFH
03000000H
02FFFFFFH
00280000H
0027FFFFH
00250000H
00200000H
00000000H
00100000H
0024FFFFH
001FFFFFH
000FFFFFH
03FEC000H
01000000H
03FEBFFFH
03FEC000H
Notes 1. CS1 is not provided as an external signal of the V850ES/Jx3-H; it is used internally as a chip select
signal for the USB.
2. Use of addresses 03FEF000H to 03FEFFFFH is prohibited because they overlap an on-chip
peripheral I/O area.
3. The programmable peripheral I/O area is seen as 256 MB areas in the 4 GB address space.
4. In on-chip CAN controller products, addresses 03FEC000H to 03FEEFFFH are assigned to
addresses 03FEC000H to 03FECBFFH as a programmable peripheral I/O area. In other products,
use of this area is prohibited.
5. This area is used as an external memory area when data write access to this area is executed.