Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER
R01UH0042EJ0500 Rev.5.00 Page 658 of 1513
Aug 12, 2011
12.4.4 Changing INTRTC0 interrupt setting during the real-time counter operation
If the setting of the INTRTC0 interrupt (fixed-cycle interrupt) signal is changed while the real-time counter clock
operates (PC1PWR = 1), the INTRCT0 interrupt waveform may include whiskers and unintended signals may be output.
Set as follows when changing the setting of the INTRTC0 interrupt signal during the real-time counter operation (RC1PWR
= 1, RTCE = 1), in order to mask the whiskers.
Figure 12-5. Changing INTRTC0 Interrupt Setting During The real-time counter Operation
Start
Setting RTC0MK bit Masks INTRTC0 interrupt signal.
Setting RC1CC1.CT2 to
RC1CC1.CT0
Changes INTRTC0 interrupt signal setting.
End
Clearing RTC0IF flag
Clears interrupt request flag.
Clearing RTC0MK flag Unmasks INTRTC0 interrupt signal.
Remark See 23.3.4 Interrupt control register (xxICn) for details of the RTC0IF and RTC0MK bits.