Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 12 REAL-TIME COUNTER
R01UH0042EJ0500 Rev.5.00 Page 642 of 1513
Aug 12, 2011
(3) Real-time counter control register 2 (RC1CC2)
The RC1CC2 register is an 8-bit register that controls the alarm interrupt function and waiting of counters.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
WALE
Does not generate interrupt upon alarm match.
Generates interrupt upon alarm match.
WALE
0
1
Alarm interrupt (INTRTC1) operation control
RC1CC2 0000
0
RWST RWAIT
654321
Counter operating
Counting up of second to year counters stopped
(Reading and writing of counter values enabled)
RWST
0
1
Real-time counter wait state
This is a status flag indicating whether the RWAIT bit setting is valid.
Read or write counter values after confirming that the RWST bit is 1.
Sets counter operation.
Stops count operation of second to year counters.
(Counter value read/write mode)
RWAIT
0
1
Real-time counter wait control
This bit controls the operation of the counters.
Be sure to write 1 to this bit when reading or writing counter values.
If the RC1SUBC register overflows while the RWAIT bit is 1, the overflow
information is retained internally and the RC1SEC register is counted up after two
clocks or less after 0 is written to the RWAIT bit.
However, if the second counter value is rewritten while the RWAIT bit is 1, the
retained overflow information is discarded.
07
After reset: 00H R/W Address: FFFFFADFH
Cautions 1. See 12.4.5 Changing INTRTC1 interrupt setting during the real-time counter operation
when rewriting the WALE bit while the real-time counter operates (RC1PWR bit = 1).
2. Confirm that the RWST bit is set to 1 when reading or writing each counter value.
3. The RWST bit does not become 0 while each counter is being written, even if the RWAIT
bit is set to 0. It becomes 0 when writing to each counter is completed.