Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 633 of 1513
Aug 12, 2011
Figure 11-38. Example of A/D Conversion Start Trigger (TABTADT0) Signal Output
(TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 1,
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 Bits = 00000: Without Interrupt Culling)
16-bit
counter
INTTAB1OV signal
INTTAA4CC0 signal
INTTAA4CC1 signal
TAB1CUF bit
TABTADT0 signal
TABTADT0 signal
TABTADT0 signal
TABTADT0 signal
TABTADT0 signal
TABTADT0 signal
TABTADT0 signal
TABTADT0 signal
TAB1AT3 to TAB1AT0 bits = 0001 (INTTAB1OV signal output)
TAB1AT3 to TAB1AT0 bits = 0010 (INTTAB1CC0 signal output)
TAB1AT3 to TAB1 AT0 bits = 0100, TAB1ATM2 bit = 0 (INTTAA4CC0 signal output during counting up)
TAB1AT3
to TAB1 AT0 bits = 0100, TAB1ATM2 bit = 1 (INTTAA4CC0 signal output during counting down)
TAB1AT3
to TAB1 AT0 bits = 1000, TAB1ATM3 bit = 1 (INTTAA4CC1 signal output during counting down)
TAB1AT3 to TAB1AT0 bits = 0011 (setting to output A/D conversion start trigger signal when both crest and valley interrupts occur)
TAB1AT3 to TAB1AT0 bits = 1100, TAB1ATM3 bit = 1, TAB1ATM2 bit = 0 (INTTAA4CC0 and INTTAA4CC1 signals ORed for output.
Setting to output A/D conversion start trigger signal when match interrupt of TAA4 occurs when counter is counting up or down)
TAB1AT3 to TAB1 AT0 bits = 1000, TAB1ATM3 bit = 0 (INTTAA4CC1 signal output during counting up)
INTTAB1CC0 signal