Datasheet
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 631 of 1513
Aug 12, 2011
11.4.6 A/D conversion start trigger output function
The V850ES/JG3-H and V850ES/JH3-H have a function to select four trigger sources (INTTAB1OV, INTTAB1CC0,
INTTAA4CC0, INTTAA4CC1) to generate the A/D conversion start trigger signal (TABTADT0).
The trigger sources are specified by the TAB1OPT2.TAB1AT0 to TAB1OPT2.TAB1AT3 bits.
• TAB1AT0 bit = 1:
A/D conversion start trigger signal generated when INTTAB1OV (counter underflow) occurs.
• TAB1AT1 bit = 1:
A/D conversion start trigger signal generated when INTTAB1CC0 (cycle match) occurs.
• TAB1AT2 bit = 1:
A/D conversion start trigger signal generated when INTTAA4CC0 (match of TAA4CCR0 register of TAA4 during
tuning operation) occurs.
• TAB1AT3 bit = 1:
A/D conversion start trigger signal generated when INTTAA4CC1 (match of TAA4CCR1 register of TAA4 during
tuning operation) occurs.
The A/D conversion start trigger signals selected by the TAB1AT0 to TAB1AT3 bits are ORed and output. Therefore, two
or more trigger sources can be specified at the same time.
The INTTAB1OV and INTTAB1CC0 signals selected by the TAB1AT0 and TAB1AT1 bits are culled interrupt signals.
Therefore, these signals are output after the interrupts have been culled and, unless interrupt output is enabled (by the
TAB1OPT1.TAB1ICE and TAB1OPT1.TAB1IOE bits), the A/D conversion start trigger signal is not output.
The trigger sources (INTTAA4CC0 and INTTAA4CC1) from TAA4 have a function to mask the A/D conversion start
trigger signal depending on the count-up/count-down status of the 16-bit counter, if so set by the TAB1AT2 and TAB1AT3
bits.
• TAB1ATM2 bit: Corresponds to the TAB1AT2 bit and controls INTTAA4CC0 (match interrupt signal) of TAA4.
• TAB1ATM2 bit = 0: The A/D conversion start trigger signal is output when the 16-bit counter counts up
(TAB1OPT0.TAB1CUF bit = 0), and the A/D conversion start trigger signal is not output when
the 16-bit counter counts down (TAB1OPT0.TAB1CUF bit = 1).
• TAB1ATM2 bit = 1: The A/D conversion start trigger signal is output when the 16-bit counter counts up
(TAB1OPT0.TAB1CUF bit = 1), and the A/D conversion start trigger signal is not output when
the 16-bit counter counts down (TAB1OPT0.TAB1CUF bit = 0).
• TAB1ATM3 bit: Corresponds to the TAB1AT3 bit and controls INTTAA4CC1 (match interrupt signal) of TAA4.
• TAB1ATM3 bit = 0: The A/D conversion start trigger signal is output when the 16-bit counter counts up
(TAB1OPT0.TAB1CUF bit = 0), and the A/D conversion start trigger signal is not output when
the 16-bit counter counts down (TAB1OPT0.TAB1CUF bit = 1).
• TAB1ATM3 bit = 1: The A/D conversion start trigger signal is output when the 16-bit counter counts up
(TAB1OPT0.TAB1CUF bit = 1), and the A/D conversion start trigger signal is not output when
the 16-bit counter counts down (TAB1OPT0.TAB1CUF bit = 0).
The TAB1ATM3, TAB1ATM2, and TAB1AT3 to TAB1AT0 bits can be rewritten while the timer is operating. If the bit that
sets the A/D conversion start trigger signal is rewritten while the timer is operating, the new setting is immediately reflected
in the output status of the A/D conversion start trigger signal. These control bits do not have a transfer function and can be
used only in the anytime rewrite mode.