Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 63 of 1513
Aug 12, 2011
3.3 Operation Modes
The V850ES/JG3-H and V850ES/JH3-H have the following operation modes.
(1) Normal operation mode
In this mode, each pin related to the bus interface is set to the port mode after system reset has been released.
Execution branches to the reset entry address of the internal ROM, and then instruction processing is started.
(2) Flash memory programming mode
In this mode, the internal flash memory can be programmed by using a flash programmer.
(3) On-chip debug mode
The V850ES/JG3-H and V850ES/JH3-H are provided with an on-chip debug function that employs the JTAG (Joint
Test Action Group) communication specifications.
For details, see CHAPTER 32 ON-CHIP DEBUG FUNCTION.
3.3.1 Specifying operation mode
Specify the operation mode by using the FLMD0 and FLMD1 pins.
In the normal mode, make sure that a low level is input to the FLMD0 pin when reset is released.
In the flash memory programming mode, a high level is input to the FLMD0 pin from the flash programmer if a flash
programmer is connected, but it must be input from an external circuit in the self-programming mode.
Operation When Reset Is Released
FLMD0 FLMD1
Operation Mode After Reset
L
×
Normal operation mode
H L Flash memory programming mode
H H Setting prohibited
Remark L: Low-level input
H: High-level input
×: Don’t care