Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 627 of 1513
Aug 12, 2011
(4) Rewriting TAB1OPT0.TAB1CMS bit
The TAB1CMS bit can select the anytime rewrite mode and batch rewrite mode. This bit can be rewritten during
timer operation (when TAB1CTL0.TAB1CE bit = 1). However, the operation and caution illustrated in Figure 11-36
are necessary.
If the TAB1CCR1 register is written when the TAB1CMS bit is cleared to 0, a transfer request signal (internal signal)
is set.
When the transfer request signal is set, the register is transferred at the next transfer timing, and the transfer
request signal is cleared. This transfer request signal is also cleared when the TAB1CMS bit is set to 1.
Figure 11-36. Rewriting TAB1CMS Bit
16-bit
counter
Transfer
request signal
Transfer
timing
<1>
<2>
<3>
<4>
<5> <6>
TAB1CCR1
register
0000H
CCR1 buffer
register
Write signal of
TAB1CCR1
Clear Clear
TAB1CMS bit
ir
rs
s
k
i
<1> If the TAB1CCR1 register is rewritten when the TAB1CMS bit is 0, the transfer request signal is set.
If the TAB1CMS bit is set to 1 in this status, the transfer request signal is cleared.
<2> The register is not transferred because the TAB1CMS bit is set to 1 and the transfer request signal is
cleared.
<3> The transfer request signal is not set even if the TAB1CCR1 register is written when the TAB1CMS bit is 1.
<4> The transfer request signal is not set even if the TAB1CCR1 register is written when the TAB1CMS bit is 1,
so even if the TAB1CMS bit is cleared to 0, transfer does not occur at the subsequent transfer timing.
<5> The transfer request signal is set if the TAB1CCR1 register is written when the TAB1CMS bit is 0.
Transfer is performed at the subsequent transfer timing and the transfer request signal is cleared.
<6> Once transfer has been performed, the transfer request signal is cleared. Therefore, transfer is not
performed at the next transfer timing.