Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 624 of 1513
Aug 12, 2011
Figure 11-33. Rewriting TAB1CCR0 Register (When Valley Interrupt Is Set)
i
L
i
i
M
0000H
0000H
M
N
N
k
k
kk
M + 1
M + 1
N + 1
i
i
i
16-bit
counter
Transfer
timing
TAB1CCR0
register
TAB1CCR1
register
CCR0 buffer
register
CCR1 buffer
register
INTTAB1CC0
signal
TOAB1T1
pin output
INTTAB1OV
signal
The transfer timing is generated when the valley interrupt occurs, the cycle of counting up becomes same as
cycle of counting down, and a symmetrical triangular wave is output.
Remarks 1. This is an example of the operation when the TAB1OPT1.TAB1ICE bit = 0, TAB1OPT1.TAB1IOE
bit = 1, and TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001.
2.
: Culled interrupt