Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 623 of 1513
Aug 12, 2011
(b) Rewriting TAB1CCR0 register
When rewriting the TAB1CCR0 register in the intermittent batch mode, the output waveform differs depending
on where the occurrence of the crest or valley interrupt is specified by the interrupt culling setting. The
following figure illustrates the change of the output waveform when interrupts are culled.
Figure 11-32. Rewriting TAB1CCR0 Register (When Crest Interrupt Is Set)
16-bit
counter
Transfer
timing
TAB1CCR0
register
TAB1CCR1
register
CCR0 buffer
register
CCR1 buffer
register
INTTAB1CC0
signal
TOAB1T1
pin output
INTTAB1OV
signal
i
L
i
M
M
0000H
0000H
M
N
N
k
k
k
k
kk
N + 1i
i
i
The transfer timing is generated when the crest interrupt occurs, the cycle of counting up and counting down
changes, and an asymmetrical triangular wave is output.
Remarks 1. This is an example of the operation when the TAB1OPT1.TAB1ICE bit = 1, TAB1OPT1.TAB1IOE
bit = 0, and TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001.
2.
: Culled interrupt