Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 622 of 1513
Aug 12, 2011
Figure 11-31. Basic Operation in Intermittent Batch Rewrite Mode
INTTAB1OV signal
INTTAB1CC0 signal
CCR2 buffer
register
CCR3 buffer
register
OPT1 buffer
register
TAB1CCR2
register
TAB1CCR3
register
TAB1OPT1
register
<Q4>
<Q4>
16-bit counter
(TAB1)
Transfer
timing
TAB1CCR0
register
TAB1CCR1
register
CCR0 buffer
register
CCR1 buffer
register
<Q1>&<P1>
<Q2>
<Q4> <Q4>
<Q3>
<Q3>
16-bit counter
(TAA4)
Transfer
timing
TAA4CCR0
register
TAA4CCR1
register
CCR0 buffer
register
CCR1 buffer
register
<P2>
<P4> <P4>
<P3>
<P3>
<Q3>
<Q3>
<Q3>
[TAB1 operation]
<Q1> Write the TAB1CCR1 register.
<Q2> Rewrite the register at the transfer timing that is generated after the TAB1CCR1 register has been
rewritten.
<Q3> The registers are transferred all at once at the transfer timing.
<Q4> The transfer timing is also culled as the interrupts are culled.
[TAA4 operation]
<P1> Write the TAB1CCR1 register.
<P2> Rewrite the register at the transfer timing that is generated after the TAB1CCR1 register has been
rewritten.
<P3> The registers are transferred all at once at the transfer timing.
<P4> The transfer timing is also culled as the interrupts are culled.
Remark This is an example of the operation when the TAB1OPT1.TAB1ICE bit = 1, TAB1OPT1.TAB1IOE bit =
1, and TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001.