Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 615 of 1513
Aug 12, 2011
(2) Batch rewrite mode (transfer mode)
This mode is set by clearing the TAB1OPT0.TAB1CMS bit to 0, the TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0
bits to 00000, and the TAB1OPT2.TAB1RDE bit to 0.
In this mode, the values written to each compare register are transferred to the internal buffer register all at once at
the transfer timing and compared with the counter value.
(a) Rewriting procedure
If data is written to the TAB1CCR1 register, the values set to the TAB1CCR0 to TAB1CCR3, TAB1OPT1,
TAA4CCR0, and TAA4CCR1 registers are transferred all at once to the internal buffer register at the next
transfer timing. Therefore, write to the TAB1CCR1 register last. Writing to the register is prohibited after the
TAB1CCR1 register has been written and before the transfer timing is generated (until the crest (match
between the 16-bit counter value and TAB1CCR0 register value) or the valley (match between the 16-bit
counter value and 0001H)). The operation procedure is as follows.
<1> Rewriting the TAB1CCR0, TAB1CCR2, TAB1CCR3, TAB1OPT1, TAA4CCR0, and TAA4CCR1 registers
Do not rewrite registers that do not have to be rewritten.
<2> Rewriting the TAB1CCR1 register
Rewrite the same value to the register even when it is not necessary to rewrite the TAB1CCR1 register.
<3> Holding the next rewriting pending until the transfer timing is generated
Rewrite the register next time after the INTTAB1OV or INTTAB1CC0 interrupt has occurred.
<4> Return to <1>.