Datasheet
V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 611 of 1513
Aug 12, 2011
(1) Anytime rewrite mode
This mode is set by setting the TAB1OPT0.TAB1CMS bit to 1. The setting of the TAB1OPT2.TAB1RDE bit is
ignored.
In this mode, the value written to each register with a transfer function is immediately transferred to an internal
buffer register and compared with the value of the counter. If a register with transfer function is rewritten in this
mode after the count value of the 16-bit counter matches the value of the TAB1CCRm register, the rewritten value
is not reflected because the next match is ignored after the first match has occurred. If the register is rewritten
during counting up, the new register value becomes valid after the counter has started counting down.
Figure 11-21. Timing of Reflecting Rewritten Value
Operating clock
(f
XX
/2)
TAB1CCR0
register
ba
CCR0 buffer
register
ba
Note
Note After the register (TAB1CCR0, TAB1CCR2, TAB1CCR3, TAB1OPT1, TAA4CCR0, or TAA4CCR1) has
been written, the written value is transferred to an internal buffer register after four clocks of the operating
clock. However, the value of the TAB1CCR1 register is transferred after 5 clocks.
(a) Rewriting TAB1CCR0 register
Even if the TAB1CCR0 register is rewritten in the anytime rewrite mode, the new value may not be reflected in
some cases.
Figure 11-22. Example of Rewriting TAB1CCR0 Register
16-bit
counter
<1> <2> <1> <2>
Rewriting during period <1> (rewriting during counting up)
If the newly rewritten value is greater than the value of the 16-bit counter, there is no problem because it will
match the value of the 16-bit counter. If the new value is less than the value of the 16-bit counter, it will not
match the value of the counter. As a result, the 16-bit counter overflows and continues counting up from
0000H until it matches the register value again, and the correct PWM waveform is not output.
Rewriting during period <2> (rewriting during counting down)
A match with the value of the 16-bit counter is ignored during counting down. Therefore, the rewritten period
value is reflected as the match point starting from counting up in the next cycle.