Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 608 of 1513
Aug 12, 2011
(3) To output only crest interrupt (INTTAB1CC0)
Set the TAB1OPT1.TAB1ICE bit to 1 and clear the TAB1OPT1.TAB1IOE bit to 0.
Figure 11-19. Crest Interrupt Output
(a) TAB1OPT0.TAB1CMS bit = 0, TAB1OPT2.TAB1RDE bit = 1 (with transfer culling control)
00010
L
00010
00011
Transfer
00011
Timing of rewriting transfer
culling count from 2 to 3
16-bit
counter
TAB1ID4 to TAB1ID0 bits
TAB1ID4 to TAB1ID0 bits
(slave bit)
INTTAB1OV
signal
INTTAB1CC0
signal
Remarks 1. Transfer is performed at the culled interrupt output timing. The other transfer timing is ignored.
2. : Culled interrupt
(b) TAB1CMS bit = 1, TAB1RDE bit = 0 or 1 (without transfer control)
00010
L
Reflected immediately
00011
00010
00011
Timing of rewriting transfer
culling count from 2 to 3
16-bit
counter
TAB1ID4 to TAB1ID0 bits
TAB1ID4 to TAB1ID0 bits
(slave bit)
INTTAB1OV
signal
INTTAB1CC0
signal
Remarks 1. Rewriting is reflected immediately. The transfer timing is ignored.
2.
: Culled interrupt