Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 602 of 1513
Aug 12, 2011
(5) Dead-time control in case of incorrect setting
Usually, the TOAB1m (internal signal) output of TAB1 changes only once during dead-time counting, only in the
vicinity of 0% and 100% output. This section shows an example where the TAB1CCR0 register (carrier cycle) and
TAB1DTC register (dead-time value) are incorrectly set. If these registers are incorrectly set, the TOAB1m (internal
signal) output of TAB1 changes twice or three times during dead-time counting. The following flowchart shows the
6-phase PWM output wave in this case.
Figure 11-14. Operation of Dead-Time Counter m (2)
(a) When TAB1OPT2.TAB1DTM bit = 0, TAB1CCR0 register = 0006H, TAB1DTC register = 000FH,
TAB1CCRm register = 0004H
Counter cleared
Counter is not cleared but continues counting
000H
001H 002H 003H 004H
005H
006H 001H 002H 003H
004H
005H 006H 007H 008H 009H 00AH 00BH 00CH 00DH 00EH 00FH
000H
001H
16-bit
counter
TOAB1m signal
(internal signal)
Dead-time
counter m
TOAB1Tm
pin output
TOAB1Bm
pin output
(b) When TAB1OPT2.TAB1DTM bit = 1, TAB1CCR0 register = 0006H, TAB1DTC register = 000FH,
TAB1CCRm register = 0002H
Starts counting
down.
Output does not change
and dead-time counter m
continues counting down
001H 002H 003H 004H 005H 006H 007H 008H 009H 00AH 009H 008H 007H 006H 005H 004H 003H 002H 001H 001H 002H 003H 004H 003H 002H 001H
000H 000H
16-bit
counter
TOAB1m signal
(internal signal)
Dead-time
counter m
TOAB1Tm
pin output
TOAB1Bm
pin output
Remark m = 1 to 3