Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 598 of 1513
Aug 12, 2011
Figure 11-10. 100% PWM Output Waveform (With Dead Time)
ii iii
i
M
i
i
i
i
0000H
0000H0000H
0000H 0000H
i
<1> <2> <3> <4>
i
100%
output
100%
output
16-bit
counter
TAB1CCR0
register
TAB1CCR1
register
TOAB1T1
pin output
TOAB1B1
pin output
CCR1
buffer register
Forced timing
of timer output
<1> 100% output is selected by the valley interrupt (with a match with the 16-bit counter).
The valley interrupt forcibly lowers the timer output, but raising the timer output takes precedence when
the value of the TAB1CCRm register matches the value of the 16-bit counter. As a result, the 100% output
is produced.
<2> 100% output is canceled by the valley interrupt (without a match with the 16-bit counter).
The valley interrupt forcibly lowers the timer output. This cancels the 100% output.
<3> 100% output is selected by the crest interrupt (without a match with the 16-bit counter).
The crest interrupt forcibly raises the timer output. This produces the 100% output.
<4> 100% output is canceled by the crest interrupt (without a match with the 16-bit counter).
The crest interrupt forcibly raises the timer output. This cancels the 100% output.
Remarks 1.
means forcible raising and means forcible lowering.
2. m = 1 to 3