Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 597 of 1513
Aug 12, 2011
(2) PWM output of 0%/100%
The V850ES/V850ES/JG3-H and V850ES/JH3-H are capable of 0% wave output and 100% wave output for PWM
output.
A low level is continuously output from the TOAB1Tm pin as the 0% wave output. A high level is continuously
output from the TOAB1Tm pin as the 100% wave output.
A 0% wave is output by setting the TAB1CCRm register to “M + 1” when the TAB1CCR0 register = M.
A 100% wave is output by setting the TAB1CCRm register to “0000H”.
Rewriting the TAB1CCRm register is enabled while the timer is operating, and 0% wave output or 100% wave
output can be selected at the point of the crest interrupt (INTTAB1CC0) and valley interrupt (INTTAB1OV).
Remark m = 1 to 3
Figure 11-9. 0% PWM Output Waveform (With Dead Time)
i
i
0% output
i
i
i
i
i
M
i
i
i
M + 1 M + 1
M + 1 M + 1
i
i
<4><3><2>
<1>
0000H
0% output
16-bit
counter
TAB1CCR0
register
TAB1CCR1
register
TOAB1T1
pin output
TOAB1B1
pin output
CCR1
buffer register
Forced timing
of timer output
<1> 0% output is selected by the valley interrupt (without a match with the 16-bit counter).
The valley interrupt forcibly lowers the timer output. This produces the 0% output.
<2> 0% output is canceled by the crest interrupt (without a match with the 16-bit counter).
The crest interrupt forcibly raises the timer output. This cancels the 0% output.
<3> 0% output is selected by the crest interrupt (with a match with the 16-bit counter).
The crest interrupt forcibly raises the timer output, but lowering the timer output takes precedence when
the value of the TAB1CCRm register matches the value of the 16-bit counter. As a result, the 0% wave is
output.
<4> 0% output is canceled by the valley interrupt (without a match with the 16-bit counter).
The valley interrupt forcibly lowers the timer output. This cancels the 0% output.
Remarks 1.
means forcible raising and means forcible lowering.
2. m = 1 to 3