Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 590 of 1513
Aug 12, 2011
(a) Setting procedure
(i) Setting of high-impedance control operation
<1> Set the HZA0DCMn, HZA0DCNn, and HZA0DCPn bits.
<2> Set the HZA0DCEn bit to 1 (enable high-impedance control).
(ii) Changing setting after enabling high-impedance control operation
<1> Clear the HZA0DCEn bit to 0 (to stop the high-impedance control operation).
<2> Change the setting of the HZA0DCMn, HZA0DCNn, and HZA0DCPn bits.
<3> Set the HZA0DCEn bit to 1 (to enable the high-impedance control operation again).
(iii) Resuming output when pins are in high-impedance state
If the HZA0DCMn bit is 1, set the HZA0DCCn bit to 1 to clear the high-impedance state after the valid
edge of the external pin is detected. However, the high-impedance state cannot be cleared unless this bit
is set while the input level of the external pin is inactive.
<1> Set the HZA0DCCn bit to 1 (command signal to clear the high-impedance state).
<2> Read the HZA0DCFn bit and check the flag status.
<3> Return to <1> if the HZA0DCFn bit is 1. The input level of the external pin must be checked.
The pin can function as an output pin if the HZA0DCFn bit is 0.
(iv) Making pin go into high-impedance state by software
The HZA0DCTn bit must be set to 1 by software to make the pin go into a high-impedance state while the
input level of the external pin is inactive. The following procedure is an example in which the setting is not
dependent upon the setting of the HZA0DCMn bit.
<1> Set the HZA0DCTn bit to 1 (high-impedance output command).
<2> Read the HZA0DCFn bit to check the flag status.
<3> Return to <1> if the HZA0DCFn bit is 0. The input level of the external pin must be checked.
The pin is in a high-impedance state if the HZA0DCFn bit is 1.
However, if the external pin is not used with the HZA0DCPn bit and HZA0DCNn bit cleared to 0, the pin
goes into a high-impedance state when the HZA0DCTn bit is set to 1.
Remark n = 0, 1