Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 588 of 1513
Aug 12, 2011
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HZA0DCCn
0
1
High-impedance output control clear bit
No operation
Pins that have gone into a high-impedance state are output-enabled by
software and the HZA0DCFn bit is cleared to 0.
• Pins can function as output pins when the HZA0DCM bit = 0, regardless of the
status of the external pin.
• If an edge indicating abnormality is input to the external pin (which is set by the
HZA0DCNn and HZA0DCPn bits) when the HZA0DCM bit = 1, the HZA0DCCn
bit is invalid even if it is set to 1.
• The HZA0DCCn bit is always 0 when it is read.
• The HZA0DCCn bit is invalid even if it is set to 1 when the HZA0DCEn bit = 0.
• Simultaneously setting the HZA0DCTn and HZA0DCCn bits to 1 is prohibited.
HZA0DCFn High-impedance output status flag
Indicates that output of the pin is enabled.
• This bit is cleared to 0 when the HZA0DCEn bit = 0.
• This bit is cleared to 0 when the HZA0DCCn bit = 1.
Indicates that the pin goes into a high-impedance state.
• This bit is set to 1 when the HZA0DCTn bit = 1.
• This bit is set to 1 when an edge indicating abnormality is input to the
external pin (which is detected according to the setting of the
HZA0DCNn and HZA0DCPn bits).
Clear (0)
Set (1)
HZA0DCTn
0
1
High-impedance output trigger bit
No operation
Pins are made to go into a high-impedance state by software and the
HZA0DCFn bit is set to 1.
• If an edge indicating abnormality is input to the external pin (which is detected
according to the setting of the HZA0DCNn and HZA0DCPn bits), the HZA0DCTn
bit is invalid even if it is set to 1.
• The HZA0DCTn bit is always 0 when it is read because it is a software-triggered
bit.
• The HZA0DCTn bit is invalid even if it is set to 1 when the HZA0DCEn bit = 0.
• Simultaneously setting the HZA0DCTn and HZA0DCCn bits to 1 is prohibited.