Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 582 of 1513
Aug 12, 2011
(2) TAB1 option register 2 (TAB1OPT2)
The TAB1OPT2 register is an 8-bit register that controls the timer Q option function.
This register can be rewritten when the TAB1CTL0.TAB1CE bit is 1. However, rewriting the TAB1DTM bit is
prohibited when the TAB1CE bit is 1. The same value can be rewritten.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
(1/2)
TAB1RDETAB1OPT2 TAB1DTM TAB1ATM3 TAB1ATM2 TAB1AT3 TAB1AT2 TAB1AT1 TAB1AT0
<6> <5> <4> <3> <2> <1>
Rewriting the TAB1DTM bit is disabled during timer operation. If it is rewritten by
mistake, stop the timer operation by clearing the TAB1CE bit to 0, and re-set the
TAB1DTM bit.
TAB1DTM
0
1
Dead-time counter operation mode selection (m = 1 to 3)
The dead-time counter counts up normally and, if TOAB1m output of
TAB1 is at a narrow interval (TOAB1m output width < dead-time width),
the dead-time counter is cleared and counts up again.
The dead-time counter counts up normally and, if TOAB1m output of
TAB1 is at a narrow interval (TOAB1m output width < dead-time width),
the dead-time counter counts down and the dead-time control width is
automatically narrowed.
After reset: 00H R/W Address: FFFFF581H
<7> <0>
TAB1RDE
0
1
Transfer culling enable
Do not cull transfer (transfer timing is generated every time at crest
and valley).
Cull transfer at the same interval as interrupt culling set by the TAB1OPT1
register.
Cautions 1. When using interrupt culling (the TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits are
set to other than 00000), be sure to set the TAB1RDE bit to 1.
This means that interrupts and transfers are generated at the same timing. Interrupts
and transfers, cannot be set separately. If interrupts and transfers are set separately
(TAB1RDE bit = 0), transfers are not performed normally.
2. When generating a dead-time period, set the TAB1DTC register to 1 or higher.
Note, when the operation is stopped (TAB1CTL0.TAB1CE bit = 0), a dead-time period is
not generated, so the output levels of the TOAB1T1 to TOAB1T3 and TOAB1B1 to
TOAB1B3 pins are in their default states. Therefore, for the protection of the system,
take measures such as making the TOAB1T1 to TOAB1T3 and TOAB1B1 to TOAB1B3
pins go into a high-impedance state before stopping operation, or setting the output
levels of the pins before switching port modes.
When a dead-time period is not needed, set the TAB1DTC register to 0.