Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 11 MOTOR CONTROL FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 580 of 1513
Aug 12, 2011
(1) TAB1 dead-time compare register (TAB1DTC)
The TAB1DTC register is a 10-bit compare register that specifies the dead-time value.
Rewriting this register is prohibited when the TAB1CTL0.TAB1CE bit = 1.
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
Caution When generating a dead-time period, set the TAB1DTC register to 1 or higher.
Note, when the operation is stopped (TAB1CTL0.TAB1CE bit = 0), a dead-time period is not
generated, so the output levels of the TOAB1T1 to TOAB1T3 and TOAB1B1 to TOAB1B3 pins are
in their default states. Therefore, for the protection of the system, take measures such as making
the TOAB1T1 to TOAB1T3 and TOAB1B1 to TOAB1B3 pins go into a high-impedance state before
stopping operation, or setting the output levels of the pins before switching port modes.
When a dead-time period is not needed, set the TAB1DTC register to 0.
TAB1DTC 000000 TAB1DTC9 to TAB1DTC0
10 9
After reset: 0000H R/W Address: FFFFF584H
15 0
(2) Dead-time counters 1 to 3
The dead-time counters are 10-bit counters that count dead time.
These counters are cleared or count up at the rising or falling edge of the TOAB1m output signal of TAB1, and are
cleared or stopped when their count value matches the value of the TAB1DTC register. The count clock of these
counters is the same as that set by the TAB1CTL0.TAB1CKS2 to TAB1CTL0.TAB1CKS0 bits of TAB1.
Remarks 1. The operation differs when the TAB1OPT2.TAB1DTM bit = 1. For details, see 11.4.2 (4) Automatic
dead-time width narrowing function (TAB1OPT2.TAB1DTM bit = 1).
2. m = 1 to 3