Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 10 16-BIT INTERVAL TIMER M (TMM)
R01UH0042EJ0500 Rev.5.00 Page 575 of 1513
Aug 12, 2011
10.4.2 Cautions
(1) It takes the 16-bit counter up to the following time to start counting after the TMnCTL0.TMnCE bit is set to 1,
depending on the count clock selected.
(n = 0)
Selected Count Clock Maximum Time Before Counting Start
fXX 2/fXX
fXX/2 3/fXX
fXX/4 6/fXX
fXX/64 128/fXX
fXX/512 1024/fXX
fXX/1024 2048/fXX
fR/8 16/fR
fXT 2/fXT
(n = 1 to 3)
Selected Count Clock Maximum Time Before Counting Start
fXX/2 4/fXX
fXX/4 6/fXX
fXX/8 12/fXX
fXX16 32/fXX
fXX/64 128/fXX
fXX/256 512/fXX
fXX/512 1024/fXX
fXX/1024 2048/fXX
(2) Rewriting the TMnCMP0 and TMnCTL0 registers is prohibited while TMMn is operating.
If these registers are rewritten while the TMnCE bit is 1, the operation cannot be guaranteed.
If they are rewritten by mistake, clear the TMnCTL0.TMnCE bit to 0, and re-set the registers.
Remark n = 0 to 3