Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 10 16-BIT INTERVAL TIMER M (TMM)
R01UH0042EJ0500 Rev.5.00 Page 574 of 1513
Aug 12, 2011
(2) Interval timer mode operation timing
Caution Do not set the TMnCMP0 register to FFFFH.
(a) Operation if TMnCMP0 register is set to 0000H
If the TMnCMP0 register is set to 0000H, the INTTMnEQ0 signal is generated at each count clock.
The value of the 16-bit counter is always 0000H.
Count clock
16-bit counter
TMnCE bit
TMnCMP0 register
INTTMnEQ0 signal
0000H
Interval time
Count clock cycle
FFFFH 0000H 0000H 0000H 0000H
Interval time
Count clock cycle
Remark n = 0 to 3
(b) Operation if TMnCMP0 register is set to N
If the TMnCMP0 register is set to N, the 16-bit counter counts up to N. The counter is cleared to 0000H in
synchronization with the next count-up timing and the INTTMnEQ0 signal is generated.
FFFFH
16-bit counter
0000H
TMnCE bit
TMnCMP0 register
INTTMnEQ0 signal
N
Interval time
(N + 1) ×
count clock cycle
Interval time
(N + 1) ×
count clock cycle
Interval time
(N + 1) ×
count clock cycle
N
Remark n = 0 to 3