Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 10 16-BIT INTERVAL TIMER M (TMM)
R01UH0042EJ0500 Rev.5.00 Page 573 of 1513
Aug 12, 2011
(1) Interval timer mode operation flow
Figure 10-5. Software Processing Flow in Interval Timer Mode
FFFFH
16-bit counter
0000H
TMnCE bit
TMnCMP0 register
INTTMnEQ0 signal
D
D D D
<1> <2>
TMnCE bit = 1
TMnCE bit = 0
Register initial setting
TMnCTL0 register
(TMnCKS0 to TMnCKS2 bits)
TMnCMP0 register
The initial setting of these registers is performed
before setting the TMnCE bit to 1.
The TMnCKS0 to TMnCKS2 bits cannot be set
at the same time when counting has been started
(TMnCE bit = 1).
The counter is initialized and counting is
stopped by clearing the TMnCE bit to 0.
START
STOP
<1> Count operation start flow
<2> Count operation stop flow
Remark n = 0 to 3