Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 10 16-BIT INTERVAL TIMER M (TMM)
R01UH0042EJ0500 Rev.5.00 Page 572 of 1513
Aug 12, 2011
When the TMnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with
the count clock, and the counter starts counting.
When the count value of the 16-bit counter matches the value of the TMnCMP0 register, the 16-bit counter is cleared to
0000H and a compare match interrupt request signal (INTTMnEQ0) is generated.
The interval can be calculated by the following expression.
Interval = (Set value of TMnCMP0 register + 1) × Count clock cycle
Figure 10-4. Register Setting for Interval Timer Mode Operation
(a) TMMn control register 0 (TMnCTL0)
0/1 0 0 0 0
TMnCTL0
0/1 0/1 0/1
TMnCKS2 TMnCKS1 TMnCKS0 TMnCE
0: Stop counting
1: Enable counting
Select count clock
(b) TMMn compare register 0 (TMnCMP0)
If the TMnCMP0 register is set to D, the interval is as follows.
Interval = (D + 1) × Count clock cycle
Remark n = 0 to 3