Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 10 16-BIT INTERVAL TIMER M (TMM)
R01UH0042EJ0500 Rev.5.00 Page 571 of 1513
Aug 12, 2011
10.4 Operation
Caution Do not set the TMnCMP0 register to FFFFH.
10.4.1 Interval timer mode
In the interval timer mode, an interrupt request signal (INTTMnEQ0) is generated at the specified interval if the
TMnCTL0.TMnCE bit is set to 1.
Figure 10-2. Configuration of Interval Timer
16-bit counter
TMnCMP0 registerTMnCE bit
Count clock
selection
Clear
Match signal
INTTMnEQ0 signal
Remark n = 0 to 3
Figure 10-3. Basic Timing of Operation in Interval Timer Mode
FFFFH
16-bit counter
0000H
TMnCE bit
TMnCMP0 register
INTTMnEQ0 signal
D
D D D D
Interval (D + 1) Interval (D + 1) Interval (D + 1) Interval (D + 1)
Remark n = 0 to 3