Datasheet
V850ES/JG3-H, V850ES/JH3-H CHAPTER 10 16-BIT INTERVAL TIMER M (TMM)
R01UH0042EJ0500 Rev.5.00 Page 570 of 1513
Aug 12, 2011
TMMn operation disabled (16-bit counter reset asynchronously).
Operation clock application stopped.
TMMn operation enabled. Operation clock application started. TMMn
operation started.
Internal clock control and internal circuit reset for TMMn are performed asynchronously
using the TMnCE bit. When the TMnCE bit is cleared to 0, the internal clock of TMMn
is disabled (fixed to low level) and 16-bit counter is reset asynchronously.
TMnCE
TMnCTL0
(n = 0 to 3)
0 0 0 0 TMnCKS2 TMnCKS1 TMnCKS0
654321
After reset: 00H R/W Address: TM0CTL0 FFFFFA80H, TM1CTL0 FFFFFA90H,
TM2CTL0 FFFFFAA0H, TM3CTL0 FFFFFAB0H
TMnCE
0
1
Internal clock operation enable/disable specification
0<7>
TMmCKS2
0
0
0
0
1
1
1
1
Count clock selectionTMmCKS1
0
0
1
1
0
0
1
1
TMmCKS0
0
1
0
1
0
1
0
1
fXX/2
f
XX/4
f
XX/8
f
XX/16
f
XX/64
f
XX/256
f
XX/512
f
XX/1024
(m = 1 to 3)
f
XX
= 48 MHz
41.7 ns
83.3 ns
167 ns
333 ns
1.33 s
5.33 s
10.7 s
21.3 s
f
XX
= 32 MHz
62.5 ns
125 ns
250 ns
500 ns
2.00 s
8.00 s
16.0 s
32.0 s
f
XX
= 24 MHz
83.3 ns
167 ns
333 ns
667 ns
2.67 s
10.7 s
21.3 s
42.7 s
fXX
fXX/2
f
XX/4
f
XX/64
f
XX/512
f
XX/1024
f
R/8
f
XT
TMmCKS2
0
0
0
0
1
1
1
1
Count clock selectionTMmCKS1
0
0
1
1
0
0
1
1
TMmCKS0
0
1
0
1
0
1
0
1
(m = 0)
f
XX
= 48 MHz
20.8 ns
41.7 ns
83.3 ns
1.33 s
10.7 s
21.3 s
36.4 s
30.5 s
f
XX
= 32 MHz
31.3 ns
62.5 ns
125 ns
2.00 s
16.0 s
32.0 s
36.4 s
30.5 s
f
XX
= 24 MHz
41.7 ns
83.3 ns
167 ns
2.67 s
21.3 s
42.7 s
36.4 s
30.5 s
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
Cautions 1. Set the TMnCKS2 to TMnCKS0 bits when the TMnCE bit = 0.
When changing the value of TMnCE from 0 to 1, it is not possible to set
the value of the TMnCKS2 to TMnCKS0 bits simultaneously.
2. Be sure to clear bits 3 to 6 to “0”.
Remark f
XX: Main clock frequency
fR: Internal oscillation clock frequency
f
XT: Subclock frequency