Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 10 16-BIT INTERVAL TIMER M (TMM)
R01UH0042EJ0500 Rev.5.00 Page 567 of 1513
Aug 12, 2011
10.2 Configuration
TMMn includes the following hardware.
Table 10-1. Configuration of TMMn
Item Configuration
Timer register 16-bit counter
Register TMMn compare register 0 (TMnCMP0)
Control register TMMn control register 0 (TMnCTL0)
Figure 10-1. Block Diagram of TMMn
TMnCTL0
Internal bus
f XX /2
f
XX /4
f
XX /8
f
XX /16
f
XX /64
f
XX /256
f
XX /512
f
XX /1024
Controller
16-bit counter
Match
Clear
INTTMnEQ0
TMnCMP0
TMnCE TMnCKS2 TMnCKS1TMnCKS0
Selector
Note
Note In TMM0, fXX, fXX/2, fXX/4, fXX/64, fXX/512, fXX/1024, fR, fXT
Remark f
XX: Main clock frequency
f
R: Internal oscillation clock frequency
f
XT: Subclock frequency
n = 0 to 3