Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 564 of 1513
Aug 12, 2011
(c) Basic timing 3
[Register setting condition]
• TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits = 11
The count value of the 16-bit counter is cleared to 0000H when its value matches the value of the CCR0
buffer register.
The count value of the 16-bit counter is cleared to 0000H when its value matches the value of the CCR1
buffer register.
• Setting of the TT0CTL2.TT0LDE bit is invalid.
• TT0IOC3.TT0SCE bit = 0, and TT0IOC3.TT0ECS1 and TT0IOC3.TT0ECS0 bits = 00
Specification of clearing the 16-bit counter when the edge of the encoder clear input signal (TECR0 pin) is
detected (no edge specified)
CM 00
CM 01 CM 01
CM 11
CM 10
TT0CCR0 register
CCR0 buffer register
INTTT0CC0 signal
TT0CCR1 register
CCR1 buffer register
INTTT0CC1 signal
TT0ESF bit
INTTT0OV signal
TT0EOF bit
TT0EUF bit
0000H
FFFFH
TT0CNT register
Clear
ClearClear
Clear
Underflow Underflow UnderflowOverflow
CM00 CM01
CM00
CM10 CM11
CM10 CM11
CM12
CM12
CM01
CM02
CM02
CM 12
CM 12
CM 02