Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 563 of 1513
Aug 12, 2011
When the 16-bit counter starts operating (TT0CE bit = 0 → 1), the set value of the TT0TCW register is
transferred to the 16-bit counter and the counter starts operating.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match
interrupt request signal (INTTT0CC0) is generated.
When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match
interrupt request signal (INTTT0CC1) is generated.
The 16-bit counter is not cleared to 0000H even when its count value matches the value of the CCRn buffer
register because the TT0ECM1 and TT0ECM0 bits = 00 (n = 0, 1).