Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)

R01UH0042EJ0500 Rev.5.00 Page 562 of 1513

Aug 12, 2011

(b) Basic timing 2

[Register setting condition]

• TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits = 00

The 16-bit counter is not cleared even when its count value matches the value of the CCRn buffer register (a

= 0, 1).

• TT0CTL2.TT0LDE bit = 0

The set value of the TT0CCR0 register is not transferred to the 16-bit counter after the counter underflows.

• TT0IOC3.TT0SCE bit = 0, and TT0IOC3.TT0ECS1 and TT0IOC3.TT0ECS0 bits = 00

Specification of clearing the 16-bit counter when the edge of the encoder clear input signal (TECR0 pin) is

detected (no edge specified)

TT0CCR0 register

CCR0 buffer register

INTTT0CC0 signal

TT0CCR1 register

CCR1 buffer register

INTTT0CC1 signal

TT0ESF bit

INTTT0OV signal

TT0EOF bit

TT0EUF bit

0000H

FFFFH

TT0CNT register

Underflow Overflow

CM00 CM01

CM00

CM10 CM11

CM12

CM01

CM02

CM11

CM02