Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 561 of 1513
Aug 12, 2011
When the 16-bit counter starts operating (TT0CE bit = 0 → 1), the set value of the TT0TCW register is
transferred to the counter and the 16-bit counter starts operating.
When the count value of the counter matches the value of the CCR0 buffer register, the compare match
interrupt request signal (INTTT0CC0) is generated. Because the TT0ECM0 bit = 1, the 16-bit counter is
cleared to 0000H if the next count operation is counting up.
When the count value of the 16-bit counter matches the value of the CCR1 buffer register, the compare match
interrupt request signal (INTTT0CC1) is generated. Because the TT0ECM1 bit = 0, the 16-bit counter is not
cleared to 0000H when its value matches that of the CCR1 buffer register.
When the TT0LDE bit = 1 and TT0ECM0 bit = 1, the counter can operate in a range from 0000H to the set
value of the TT0CCR0 register.