Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)

R01UH0042EJ0500 Rev.5.00 Page 560 of 1513

Aug 12, 2011

(2) Encoder compare mode operation timing

(a) Basic timing 1

[Register setting conditions]

• TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits = 01

The 16-bit counter is cleared to 0000H when its count value matches the value of the CCR0 buffer register.

• TT0CTL2.TT0LDE bit = 1

The set value of the TT0CCR0 register is transferred to the 16-bit counter when it overflows.

• TT0IOC3.TT0SCE bit = 0, and TT0IOC3.TT0ECS1 and TT0IOC3.TT0ECS0 bits = 00

Specification of clearing the 16-bit counter when the edge of the encoder clear input signal (TECR0 pin) is

detected (no edge specified)

CM00

TT0CCR0 register

CCR0 buffer register

INTTT0CC0 signal

TT0CCR1 register

CCR1 buffer register

INTTT0CC1 signal

TT0ESF bit

INTTT0OV signal

TT0EOF bit

TT0EUF bit

0000H

FFFFH

TT0CNT register

Clear

Clear Clear

Transfer

CM12

CM01